Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit.
| EN | Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. |
| P | Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. |
| S | Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. |
| ADDR | Limit address bits 31:5. Readable from any Privileged context, if and only if this region’s S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. |